The present invention relates generally to “power-on reset” (POR) circuits, particularly to a power-on reset circuit which dissipates very little power, occupies a very small amount of integrated circuit chip area, and rapidly discharges a storage capacitor that establishes a delay between an interruption in power supply voltage and an edge of a power-on reset signal generated by the power-on reset circuit.
A POR circuit resets circuitry, especially digital logic circuitry, when the power supply voltage falls below a minimum acceptable operating voltage. Preferably, a POR circuit should occupy as little integrated circuit chip area as possible. It should also consume as little power and draw as little current (e.g., less than 500 nanoamperes) from the power supply. Preferably, a POR circuit should not generate a POR output signal in response to minor fluctuations of the power supply voltage.
Power-on reset (POR) circuit 1 in Prior Art FIG. 1A has been widely used by the present assignee and others. POR reset circuit 1 includes a P-channel transistor MP0 having its source connected to VDD, its gate connected to ground, and its drain connected to one terminal of a resistor R1. The other terminal of resistor R1 is connected by conductor 2 to one terminal of a resistor R0, one terminal of a discharge capacitor C0, and the input of a first inverter 3. The other terminal of discharge capacitor C0 is connected to ground. The other terminal of resistor R0 is connected to the drain of an N-channel transistor MN0, the source of which is connected to ground. The output of inverter 3 is connected to the input of a second inverter 4, the output of which is connected by conductor 6 to the input of a third inverter 5. Inverter 4 generates a power-on reset voltage VPOR on conductor 6. The output of inverter 5 is connected by conductor 7 to the gate of transistor MN0. This eliminates current from flowing through the branch formed by MP0, R1, R0, and MN0 in FIG. 1A. The upper and lower bias terminals of inverters 3, 4 and 5 are connected to VDD and ground, respectively.
FIG. 1B shows an equivalent circuit representation of the left branch of POR circuit 1 of FIG. 1A for the case in which the power supply voltage VDD is interrupted and falls to ground. In this case, the VDD terminal of the power supply would appear as a short circuit to ground. P-channel transistor MP0 is represented by its “channel off” resistance Rds connected in parallel with its drain-bulk diode. N-channel transistor MN0 is also represented by its “channel off” resistance Rds connected in parallel with its drain-bulk diode.
Discharge capacitor C0 along with resistor R1, on-resistance of MP0 in parallel with resistor R0, and on-resistance of MN0 in Prior Art FIGS. 1A and 1B create a time constant which introduces a delay between the time at which supply voltage VDD ramps up and the time at which VPOR makes a transition from a logic low “0” level to a logic high “1” level. Once that transition occurs, transistor MN0 is turned off. If there is an interruption in the supply voltage VDD, transistors MP0 and MN0 will be turned off. The charge on discharge capacitor C0 cannot be removed in a short period of time since the effective impedances of transistors MP0 and MN0 are extremely large. This prevents the prior art POR circuit 1 from producing an adequate response by the output voltage VPOR to an interruption of VDD.
Although prior art POR circuit 1 of FIGS. 1A and 1B always works in response to an initial application of a normal value of supply voltage VDD, it requires as much as 10 or more seconds to remove the charge from discharge capacitor C0 when a sudden interruption of VDD occurs. This is because transistor MP0 is turned off and discharge transistor MN0 remains turned off by inverter 5. Hence, most of the discharging of capacitor C0 occurs through the drain-bulk diodes of transistors MP0 and MN0. As discharging of capacitor C0 progresses, the effective impedances of the drain-bulk diodes of transistors MP0 and MN0 through which the discharging occurs continue to increase. This results in the previously mentioned long delay before power-on reset signal VPOR transitions from a logic high “1” level to a logic low “0” level in response to the interruption of VDD.
The waveforms for POR circuit 1 of Prior Art FIG. 1A are somewhat similar to those shown in subsequently described FIGS. 4A-C in response to a ramp-up and/or ramp-down of VDD. However, the response of POR circuit 1 to a ramp-down of VDD is very slow, due to the previously described extremely slow discharge of capacitor C0.
Thus, there is an unmet need for a power-on reset circuit that rapidly discharges a storage capacitor that determines a delay between an interruption or loss of power supply voltage and an edge of a power-on reset signal generated by the power-on reset circuit.
There also is an unmet need for a power-on reset circuit that rapidly discharges a storage capacitor that determines a delay between an interruption or loss of power supply voltage and an edge of a power-on reset signal generated by the power-on reset circuit and dissipates very little power.
There also is an unmet need for a power-on reset circuit that rapidly discharges a storage capacitor that determines a delay between an interruption or loss of power supply voltage and an edge of a power-on reset signal generated by the power-on reset circuit, occupies a very small amount of integrated circuit chip area, and dissipates very little power.
There also is an unmet need for a power-on reset circuit that rapidly discharges a storage capacitor that determines a delay between an interruption or loss of power supply voltage and an edge of a power-on reset signal generated by the power-on reset circuit, occupies a very small amount of integrated circuit chip area, dissipates very little power, and does not generate a power-on reset output signal in response to minor fluctuations in the power supply voltage.